Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be programmed with configuration data to provide various user-defined features. For example, it is often desirable for users to program PLDs with particular input/output (I/O) functionality to support communication and interfacing of the PLDs with other devices as may be desired. As a result, significant numbers of user-programmable I/O pins may be needed to support such user-defined functionality in particular applications.
Unfortunately, certain conventional PLDs may use large numbers of I/O pins to implement manufacturer-specific programming interfaces to support the programming of the PLDs with configuration data from external computing devices. For example, such programming interfaces may be used to program memory of a PLD with configuration data to support non-volatile storage and internal transfer to the PLD's configuration memory.
Nevertheless, such programming interfaces often require the use of dedicated I/O pins. Because of the limited number of pins available on a given PLD, the use of dedicated programming interface pins can significantly reduce the number of I/O pins available for user-defined operation. Moreover, existing PLDs that may support more simplified programming interfaces with lower pin counts typically do not provide convenient ways to selectively boot from various available sources of configuration data, or they require use of interfaces that may not conveniently interface with external non-volatile memories (e.g., a JTAG interface). Accordingly, there is a need for an improved approach to the configuration of PLDs that, for example, provides users with ample I/O pins and permits configuration of the PLD to be performed through a convenient programming interface.